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Invalid register operand when updating

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Date Version Revision 10/01/02 1.0 Xilinx EDK 3.1 release 03/11/03 2.0 Xilinx EDK 3.2 release 09/24/03 3.0 Xilinx EDK 6.1 release 02/20/04 3.1 Xilinx EDK 6.2 release 08/24/04 4.0 Xilinx EDK 6.3 release 09/21/04 4.1 Minor corrections for EDK 6.3 SP1 release 11/18/04 4.2 Minor corrections for EDK 6.3 SP2 release 01/20/05 5.0 Xilinx EDK 7.1 release 04/02/05 5.1 Minor corrections for EDK 7.1 SP1 release 05/09/05 5.2 Minor corrections for EDK 7.1 SP2 release 10/05/05 5.3 Minor corrections for EDK 8.1 release 02/21/06 5.4 Corrections for EDK 8.1 SP2 release 06/01/06 6.0 Xilinx EDK 8.2 release UG081 (v14.1) Blaze Processor Reference Guide 07/24/06 6.1 Minor corrections for EDK 8.2 SP1 release 08/21/06 6.2 Minor corrections for EDK 8.2 SP2 release 08/29/06 6.3 Minor corrections for EDK 8.2 SP2 release 09/15/06 7.0 Xilinx EDK 9.1 release 02/22/07 7.1 Minor corrections for EDK 9.1 SP1 release 03/27/07 7.2 Minor corrections for EDK 9.1 SP2 release 06/25/07 8.0 Xilinx EDK 9.2 release 10/12/07 8.1 Minor corrections for EDK 9.2 SP2 release 01/17/08 9.0 Xilinx EDK 10.1 release 03/04/08 9.1 Minor corrections for EDK 10.1 SP1 release 05/14/08 9.2 Minor corrections for EDK 10.1 SP2 release 07/14/08 9.3 Minor corrections for EDK 10.1 SP3 release 02/04/09 10.0 Xilinx EDK 11.1 release 04/15/09 10.1 Xilinx EDK 11.2 release 05/28/09 10.2 Xilinx EDK 11.3 release 10/26/09 10.3 Xilinx EDK 11.4 release 04/19/10 11.0 Xilinx EDK 12.1 release 07/23/10 11.1 Xilinx EDK 12.2 release 09/21/10 11.2 Xilinx EDK 12.3 release 11/15/10 11.3 Minor corrections for EDK 12.4 release 11/15/10 11.4 Xilinx EDK 12.4 release 03/01/11 12.0 Xilinx EDK 13.1 release 06/22/11 13.2 Xilinx EDK 13.2 release 10/19/11 13.3 Xilinx EDK 13.3 release 01/18/12 13.4 Xilinx EDK 13.4 release 04/24/12 14.1 Xilinx EDK 14.1 release Date Version Revision Micro Blaze Processor Reference Guide (v14.1) Micro Blaze Processor Reference Guide UG081 (v14.1) Revision History .

The intended usage model for this port is a preemptive scheduler.

This means the port is not optimized for use as a non-preemptive scheduler and probably doesn't even support co-routines.

When Micro Blaze is configured to use an MMU (C_USE_MMU =1) this instruction is privileged.

When using wdc.flush in a loop to flush the entire cache, the loop can be optimized by using Ra as the cache base address and Rb as the loop counter: addik r5,r0, C_DCACHE_BASEADDR addik r6,r0, C_DCACHE_BYTE_SIZE-C_DCACHE_LINE_LEN*4 loop: wdc.flush r5,r6 bgtid r6,loop addik r6,r6,-C_DCACHE_LINE_LEN*4 When using wdc.clear in a loop to invalidate a memory area in the cache, the loop can be optimized by using Ra as the memory area base address and Rb as the loop counter: addik r5,r0,memory_area_base_address addik r6,r0,memory_area_byte_size-C_DCACHE_LINE_LEN*4 loop: wdc.clear r5,r6 bgtid r6,loop addik r6,r6,-C_DCACHE_LINE_LEN*4 Micro Blaze Processor Reference Guide UG081 (v14.1) Instructions wic Write to Instruction Cache Description Write into the instruction cache tag to invalidate a cache line. Register r A contains the address of the affected cache line.

cacheline_mask] cacheline_addr ÷ address & 0xffffffe0 if F = 1 and cacheline. The address of the affected cache line is always the physical address, independent of the parameter C_USE_MMU and whether the MMU is in virtual mode or real mode.

Pseudocode if MSR[UM] = 1 then ESR[EC] ÷ 00111 else if C_DCACHE_USE_WRITEBACK = 1 then address ÷ (Ra) (Rb) else address ÷ (Ra) if C_DCACHE_LINE_LEN = 4 then cacheline_mask ÷ (1 5) . Valid[i] then Mem(cacheline_addr i * 4) ÷ cacheline. Using this instruction ensures that other cache lines are not inadvertently invalidated, erroneously discarding data that has not yet been written to memory.

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The contents of register r A are XOR’ed with the extended IMM field; the result is placed into register r D.

Pseudocode (r D) ÷ (r A) © (r B) Registers Altered - r D Latency - 1 cycle xor r D, r A, r B 1 0 0 0 1 0 r D r A r B 0 0 0 0 0 0 0 0 0 0 0 0 6 1 1 1 6 2 1 3 1 Micro Blaze Processor Reference Guide UG081 (v14.1) Instructions xori Logical Exclusive OR with Immediate Description The IMM field is extended to 32 bits by concatenating 16 0-bits on the left.

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Invalid register operand when updating introduction

Invalid register operand when updating

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